By Juan J. Becerra, Eby G. Friedman
Analog layout concerns in electronic VLSI Circuits and Systems brings jointly in a single position very important contributions and up to date learn ends up in this fast paced region.
Analog layout concerns in electronic VLSI Circuits and Systems serves as a good reference, supplying perception into the most hard learn matters within the field.
Read or Download Analog Design Issues in Digital VLSI Circuits and Systems: A Special Issue of Analog Integrated Circuits and Signal Processing, An International Journal Volume 14, Nos. 1/2 (1997) PDF
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Extra info for Analog Design Issues in Digital VLSI Circuits and Systems: A Special Issue of Analog Integrated Circuits and Signal Processing, An International Journal Volume 14, Nos. 1/2 (1997)
Consider a larger circuit, a 16-bit multiplier in CMOS technology. It is built of 8 half- and 48 full- 4 . JJ. lt) f v/V /( 0. 0n t/s Fig. 16. output node outl. SO / 307. SOn 310. OOn 312. SOn t/s Fig. 17. Results of a mixed-mode-simulation. 5 0. 0 ··-' 302. SOn 30S. OOn 5 . 00n t/s Fig. 14. Output voltage ofEXOR gate. inl o----1 in2o----t adders, with 2464 transistors and 1250 nodes. For BRASIL, 20 subcircuits together with 300 transistors are chosen to be simulated with the circuit simulator.
7. Examples As a first example a small logic circuit is simulated. Figure 13 shows the schematic of an exclusive-or gate in CMOS technology. This realization of an EXOR needs just 6 transistors, but may cause problems in a timing simulation with an event-driven algorithm. The states of the nodes in a circuit depend on the states of the transistors. These have to be determined by the states of their gate-terminals. It can be seen from Figure 13, that all nodes are part of the subcircuit, which should be simulated with the knowledge of the transistor states only.
These expressions are accurate to within 25% of SPICE for a wide variety of RC loads. Furthermore, since the output waveform of this circuit is accurately modeled, the short-circuit power dissipation of the following CMOS stage loading the interconnect line can be accurately estimated to within 15% for highly resistive loads. The resistive power dissipation can be modeled to within 15% error for RC Delay and Power Expressions 37 Table III. 8 tLm CMOS technology). 1 ps to 1 ns. Therefore, due to the simplicity and accuracy of these expressions, the delay and power characteristics of a CMOS inverter driving a high impedance R C interconnect line can be efficiently estimated.
Analog Design Issues in Digital VLSI Circuits and Systems: A Special Issue of Analog Integrated Circuits and Signal Processing, An International Journal Volume 14, Nos. 1/2 (1997) by Juan J. Becerra, Eby G. Friedman